The present invention relates to a data processing system for processing information/data, and more particularly to a bus access control technique for realizing higher efficiency in processing operations in a data processing system having a hierarchical bus structure including superordinate and subordinate buses.
In information equipment such as mobile terminal apparatuses and vehicle-mounted information apparatuses, it is required to process audio signal information and image signal information. For processing a plurality of kinds of information in a unified fashion, a multimedia system LSI device (large-scale integrated circuit device) is used in these information equipment. The multimedia system LSI device includes a variety of circuit modules for such purposes as image compression, image data processing, image display, and audio data processing. In common applications, data necessary for processing operations in the circuit modules are stored into a clock-synchronous-type dynamic random access memory (SDRAM), for example. In order to make access to the SDRAM, each circuit module is coupled to the SDRAM through use of internal buses and an SDRAM controller.
Access contention occurs when a plurality of access requests are issued in parallel from a plurality of circuit modules to the SDRAM via the internal buses. A bus controller is provided for arbitration of these competing access requests. As bus access request arbitration techniques, there are known fixed-priority arbitration and round-robin arbitration schemes, for example. In the fixed-priority arbitration scheme, priority levels are preassigned to respective circuit modules, and a bus access right is given to a circuit module having the highest priority level in comparison at the time of access contention. In the round-robin arbitration scheme, priority levels for bus access requests from respective circuit modules are updated sequentially so that the lowest priority level is given to a circuit module after each execution of bus access therefrom.
In the bus access request arbitration schemes mentioned above, however, there may arise a disadvantage that a circuit module having a comparatively lower priority level is not allowed to make bus access for a long period of time to cause an interrupted operation, resulting in a possible decrease in the efficiency of processing.
In Patent Document 1 (Japanese Unexamined Patent Publication No. 2008-203989) and Patent Document 2 (Japanese Unexamined Patent Publication No. 2003-167842), there are disclosed system configurations for adjusting waiting time lengths of respective circuit modules. In the system configuration disclosed in the Patent Document 1 wherein there are provided bus masters for issuing bus access requests and a bus slave for receiving a bus access request from a bus master, a bus access request is selected according to a bus access waiting time length of each bus master. This system configuration is intended to average waiting time lengths of respective bus masters by granting a bus access right to each bus master according to a waiting time length thereof.
In the system configuration disclosed in the Patent Document 2, a bus bridge is disposed between a first bus and a second bus. Each of the first and second buses is coupled with a plurality of agents. A transaction processing count of each agent is monitored in the bus bridge, and a priority level of each agent at the time of issuance of a bus access request therefrom is adjusted according to the transaction processing count thereof. This system configuration is intended to shorten a waiting time length of an agent having a comparatively lower priority level by decreasing a priority level of an agent having a comparatively higher value in the transaction processing count thereof.
Patent Document 1:
    Japanese Unexamined Patent Publication No. 2008-203989Patent Document 2:    Japanese Unexamined Patent Publication No. 2003-167842